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M28W320BT M28W320BB
32 Mbit (2Mb x16, Boot Block) 3V Supply Flash Memory
FEATURES SUMMARY s SUPPLY VOLTAGE - VDD = 2.7V to 3.6V Core Power Supply - VDDQ= 1.65V to 3.6V for Input/Output - VPP = 12V for fast Program (optional)
s s
FBGA
Figure 1. Packages
ACCESS TIME: 70, 85, 90,100ns PROGRAMMING TIME - 10s typical - Double Word Programming Option
TFBGA47 (ZB) 6.39 x 10.5mm
s
COMMON FLASH INTERFACE - 64 bit Security Code MEMORY BLOCKS - Parameter Blocks (Top or Bottom location) - Main Blocks
s
s
BLOCK PROTECTION on TWO PARAMETER BLOCKS - WP for Block Protection AUTOMATIC STAND-BY MODE PROGRAM and ERASE SUSPEND 100,000 PROGRAM/ERASE CYCLES per BLOCK ELECTRONIC SIGNATURE - Manufacturer Code: 20h - Top Device Code, M28W320BT: 88BCh - Bottom Device Code, M28W320BB: 88BDh
TSOP48 (N) 12 x 20mm
s s s
s
May 2002
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TABLE OF CONTENTS SUMMARY DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Figure 2. Logic Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Table 1. Signal Names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Figure 3. TSOP Connections. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Figure 4. TFBGA Connections (Top view through package) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Figure 5. Block Addresses. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 SIGNAL DESCRIPTIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Address Inputs (A0-A20). . . . . . . . Data Input/Output (DQ0-DQ15). . . Chip Enable (E). . . . . . . . . . . . . . . Output Enable (G). . . . . . . . . . . . . Write Enable (W). . . . . . . . . . . . . . Write Protect (WP). . . . . . . . . . . . . Reset (RP). . . . . . . . . . . . . . . . . . . VDD Supply Voltage . . . . . . . . . . . . VDDQ Supply Voltage. . . . . . . . . . . VPP Program Supply Voltage . . . . VSS Ground. . . . . . . . . . . . . . . . . . ....... ....... ....... ....... ....... ....... ....... ....... ....... ....... ....... ...... ...... ...... ...... ...... ...... ...... ...... ...... ...... ...... ....... ....... ....... ....... ....... ....... ....... ....... ....... ....... ....... ...... ...... ...... ...... ...... ...... ...... ...... ...... ...... ...... ....... ....... ....... ....... ....... ....... ....... ....... ....... ....... ....... ...... ...... ...... ...... ...... ...... ...... ...... ...... ...... ...... ...... ...... ...... ...... ...... ...... ...... ...... ...... ...... ...... .....9 .....9 .....9 .....9 .....9 .....9 .....9 .....9 .....9 .....9 .....9
BUS OPERATIONS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Read. . . . . . . . . . . . . . . . . . Write. . . . . . . . . . . . . . . . . . Output Disable. . . . . . . . . . Standby. . . . . . . . . . . . . . . Automatic Standby. . . . . . . Reset. . . . . . . . . . . . . . . . . Table 2. Bus Operations . . ...... ...... ...... ...... ...... ...... ...... ....... ....... ....... ....... ....... ....... ....... ...... ...... ...... ...... ...... ...... ...... ....... ....... ....... ....... ....... ....... ....... ...... ...... ...... ...... ...... ...... ...... ....... ....... ....... ....... ....... ....... ....... ...... ...... ...... ...... ...... ...... ...... . . . . . . . . . . 10 . . . . . . . . . . 10 . . . . . . . . . . 10 . . . . . . . . . . 10 . . . . . . . . . . 10 . . . . . . . . . . 10 . . . . . . . . . . 10
COMMAND INTERFACE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Read Memory Array command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Read Status Register Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Read Electronic Signature Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Read CFI Query Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Block Erase Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Program Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Double Word Program Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Clear Status Register Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Program/Erase Suspend Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Program/Erase Resume Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Block Protection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Table 3. Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Table 4. Read Electronic Signature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Table 5. Memory Blocks Protection Truth Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
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Table 6. Program, Erase Times and Program/Erase Endurance Cycles . . . . . . . . . . . . . . . . . . . . 14 STATUS REGISTER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Program/Erase Controller Status (Bit 7) . . . Erase Suspend Status (Bit 6) . . . . . . . . . . . Erase Status (Bit 5) . . . . . . . . . . . . . . . . . . . Program Status (Bit 4) . . . . . . . . . . . . . . . . . VPP Status (Bit 3). . . . . . . . . . . . . . . . . . . . . Program Suspend Status (Bit 2) . . . . . . . . . Block Protection Status (Bit 1). . . . . . . . . . . Reserved (Bit 0). . . . . . . . . . . . . . . . . . . . . . Table 7. Status Register Bits . . . . . . . . . . . . ...... ...... ...... ...... ...... ...... ...... ...... ...... ....... ....... ....... ....... ....... ....... ....... ....... ....... ...... ...... ...... ...... ...... ...... ...... ...... ...... ....... ....... ....... ....... ....... ....... ....... ....... ....... ...... ...... ...... ...... ...... ...... ...... ...... ...... ...... ...... ...... ...... ...... ...... ...... ...... ...... . . . . 15 . . . . 15 . . . . 15 . . . . 15 . . . . 15 . . . . 15 . . . . 16 . . . . 16 . . . . 16
MAXIMUM RATING. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Table 8. Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 DC and AC PARAMETERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Table 9. Operating and AC Measurement Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Figure 6. AC Measurement I/O Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Figure 7. AC Measurement Load Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Table 10. Device Capacitance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Table 11. DC Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Figure 8. Read AC Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Table 12. Read AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Figure 9. Write AC Waveforms, Write Enable Controlled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Table 13. Write AC Characteristics, Write Enable Controlled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Figure 10. Write AC Waveforms, Chip Enable Controlled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Table 14. Write AC Characteristics, Chip Enable Controlled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Figure 11. Power-Up and Reset AC Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Table 15. Power-Up and Reset AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 PACKAGE MECHANICAL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Figure 12. TSOP48 - 48 lead Plastic Thin Small Outline, 12 x 20mm, Package Outline . . . . . . . . 26 Table 16. TSOP48 - 48 lead Plastic Thin Small Outline, 12 x 20mm, Package Mechanical Data . 26 Figure 13. TFBGA47 6.39x10.5mm - 8x6 ball array, 0.75mm pitch, Bottom View Package Outline27 Table 17. TFBGA47 6.39x10.5mm - 8x6 ball array, 0.75mm pitch, Package Mechanical Data . . . 27 Figure 14. TFBGA47 Daisy Chain - Package Connections (Top view through package) . . . . . . . . 28 Figure 15. TFBGA47 Daisy Chain - PCB Connections proposal (Top view through package) . . . . 28 PART NUMBERING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Table 18. Ordering Information Scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Table 19. Daisy Chain Ordering Scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 REVISION HISTORY. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Table 20. Document Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
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APPENDIX A. BLOCK ADDRESS TABLES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 Table 21. Top Boot Block Addresses, M28W320BT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 Table 22. Bottom Boot Block Addresses, M28W320BB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 APPENDIX B. COMMON FLASH INTERFACE (CFI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 Table 23. Query Structure Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 Table 24. CFI Query Identification String . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 Table 25. CFI Query System Interface Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 Table 26. Device Geometry Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 Table 27. Primary Algorithm-Specific Extended Query Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 Table 28. Security Code Area . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 APPENDIX C. FLOWCHARTS AND PSEUDO CODES. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 Figure 16. Program Flowchart and Pseudo Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 Figure 17. Double Word Program Flowchart and Pseudo Code . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 Figure 18. Program Suspend & Resume Flowchart and Pseudo Code . . . . . . . . . . . . . . . . . . . . . 39 Figure 19. Erase Flowchart and Pseudo Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 Figure 20. Erase Suspend & Resume Flowchart and Pseudo Code. . . . . . . . . . . . . . . . . . . . . . . . 41 APPENDIX D. COMMAND INTERFACE AND PROGRAM/ERASE CONTROLLER STATE . . . . . . . 42 Table 29. Write State Machine Current/Next . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
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SUMMARY DESCRIPTION The M28W320B is a 32 Mbit (2 Mbit x 16) non-volatile Flash memory that can be erased electrically at the block level and programmed in-system on a Word-by-Word basis. These operations can be performed using a single low voltage (2.7 to 3.6V) supply. VDDQ allows to drive the I/O pin down to 1.65V. An optional 12V VPP power supply is provided to speed up customer programming. The device features an asymmetrical blocked architecture. The M28W320B has an array of 71 blocks: 8 Parameter Blocks of 4 KWord and 63 Main Blocks of 32 KWord. M28W320BT has the Parameter Blocks at the top of the memory address space while the M28W320BB locates the Parameter Blocks starting from the bottom. The memory maps are shown in Figure 5, Block Addresses. Parameter blocks 0 and 1 can be protected from accidental programming or erasure. Each block can be erased separately. Erase can be suspended in order to perform either read or program in any other block and then resumed. Program can be suspended to read data in any other block and then resumed. Each block can be programmed and erased over 100,000 cycles. Program and Erase commands are written to the Command Interface of the memory. An on-chip Program/Erase Controller takes care of the timings necessary for program and erase operations. The end of a program or erase operation can be detected and any error conditions identified. The command set required to control the memory is consistent with JEDEC standards. The memory is offered in TSOP48 (10 X 20mm), and TFBGA47 (6.39 x 10.5mm, 0.75mm pitch) packages and is supplied with all the bits erased (set to '1').
Figure 2. Logic Diagram
VDD VDDQ VPP 21 A0-A20 DQ0-DQ15 W E G RP WP M28W320BT M28W320BB 16
VSS
AI03822
Table 1. Signal Names
A0-A20 DQ0-DQ15 E G W RP WP VDD VDDQ VPP VSS Address Inputs Data Input/Output Chip Enable Output Enable Write Enable Reset Write Protect Core Power Supply Power Supply for Input/Output Optional Supply Voltage for Fast Program & Erase Ground
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Figure 3. TSOP Connections
A15 A14 A13 A12 A11 A10 A9 A8 NC A20 W RP VPP WP A19 A18 A17 A7 A6 A5 A4 A3 A2 A1
1
48
12 M28W320BT 37 13 M28W320BB 36
24
25
A16 VDDQ VSS DQ15 DQ7 DQ14 DQ6 DQ13 DQ5 DQ12 DQ4 VDD DQ11 DQ3 DQ10 DQ2 DQ9 DQ1 DQ8 DQ0 G VSS E A0
AI04383
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Figure 4. TFBGA Connections (Top view through package)
1 2 3 4 5 6 7 8
A
A13
A11
A8
VPP
WP
A19
A7
A4
B
A14
A10
W
RP
A18
A17
A5
A2
C
A15
A12
A9
A20
A6
A3
A1
D
A16
DQ14
DQ5
DQ11
DQ2
DQ8
E
A0
E
VDDQ
DQ15
DQ6
DQ12
DQ3
DQ9
DQ0
VSS
F
VSS
DQ7
DQ13
DQ4
VDD
DQ10
DQ1
G
AI03823
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Figure 5. Block Addresses
M28W320BT Top Boot Block Addresses
M28W320BB Bottom Boot Block Addresses
1FFFFF 4 KWords 1FF000 Total of 8 4 KWord Blocks 1F8FFF 4 KWords 1F8000 1F7FFF 32 KWords 1F0000
1FFFFF 32 KWords 1F8000 1F7FFF 32 KWords 1F0000 Total of 63 32 KWord Blocks
00FFFF 32 KWords 008000 007FFF 4 KWords Total of 63 32 KWord Blocks 007000 Total of 8 4 KWord Blocks 000FFF 32 KWords 4 KWords 000000
00FFFF 32 KWords 008000 007FFF 000000
AI04382
Note: Also see Appendix A, Tables 21 and 22 for a full listing of the Block Addresses.
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SIGNAL DESCRIPTIONS See Figure 2 Logic Diagram and Table 1,Signal Names, for a brief overview of the signals connected to this device. Address Inputs (A0-A20). The Address Inputs select the cells in the memory array to access during Bus Read operations. During Bus Write operations they control the commands sent to the Command Interface of the internal state machine. Data Input/Output (DQ0-DQ15). The Data I/O outputs the data stored at the selected address during a Bus Read operation or inputs a command or data to be programmed during a Write Bus operation. Chip Enable (E). The Chip Enable input activates the memory control logic, input buffers, decoders and sense amplifiers. When Chip Enable is at VILand Reset is at VIH the device is in active mode. When Chip Enable is at VIH the memory is deselected, the outputs are high impedance and the power consumption is reduced to the stand-by level. Output Enable (G). The Output Enable controls data outputs during the Bus Read operation of the memory. Write Enable (W). The Write Enable controls the Bus Write operation of the memory's Command Interface. The data and address inputs are latched on the rising edge of Chip Enable, E, or Write Enable, W, whichever occurs first. Write Protect (WP). Write Protect is an input to protect or unprotect the two lockable parameter blocks. When Write Protect is at VIL, the lockable blocks are protected and Program or Erase operations are not possible. When Write Protect is at VIH, the lockable blocks are unprotected and can be programmed or erased (refer to Table 4, Memory Blocks Protection Truth). Reset (RP). The Reset input provides a hardware reset of the memory. When Reset is at VIL, the memory is in reset mode: the outputs are high impedance and the current consumption is mini-
mized. When Reset is at VIH, the device is in normal operation. Exiting reset mode the device enters read array mode, but a negative transition of Chip Enable or a change of the address is required to ensure valid data outputs. VDD Supply Voltage. VDD provides the power supply to the internal core of the memory device. It is the main power supply for all operations (Read, Program and Erase). VDDQ Supply Voltage. VDDQ provides the power supply to the I/O pins and enables all Outputs to be powered independently from VDD. VDDQ can be tied to VDD or can use a separate supply. VPP Program Supply Voltage. VPP is both a control input and a power supply pin. The two functions are selected by the voltage range applied to the pin. The Supply Voltage VDD and the Program Supply Voltage VPP can be applied in any order. If VPP is kept in a low voltage range (0V to 3.6V) VPP is seen as a control input. In this case a voltage lower than VPPLK gives an absolute protection against program or erase, while VPP > VPP1 enables these functions (see Table 11, DC Characteristics for the relevant values). VPP is only sampled at the beginning of a program or erase; a change in its value after the operation has started does not have any effect and program or erase operations continue. If VPP is in the range 11.4V to 12.6V it acts as a power supply pin. In this condition VPP must be stable until the Program/Erase algorithm is completed (see Table 13 and 14). VSS Ground. VSS is the reference for all voltage measurements. Note: Each device in a system should have VDD,VDDQ and VPP decoupled with a 0.1F capacitor close to the pin. See Figure 7, AC Measurement Load Circuit. The PCB trace widths should be sufficient to carry the required VPP Program and Erase currents.
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BUS OPERATIONS There are six standard bus operations that control the device. These are Bus Read, Bus Write, Output Disable, Standby, Automatic Standby and Reset. See Table 2, Bus Operations, for a summary. Typically glitches of less than 5ns on Chip Enable or Write Enable are ignored by the memory and do not affect bus operations. Read. Read Bus operations are used to output the contents of the Memory Array, the Electronic Signature, the Status Register and the Common Flash Interface. Both Chip Enable and Output Enable must be at VIL in order to perform a read operation. The Chip Enable input should be used to enable the device. Output Enable should be used to gate data onto the output. The data read depends on the previous command written to the memory (see Command Interface section). See Figure 8, Read Mode AC Waveforms, and Table 12, Read AC Characteristics, for details of when the output becomes valid. Read mode is the default state of the device when exiting Reset or after power-up. Write. Bus Write operations write Commands to the memory or latch Input Data to be programmed. A write operation is initiated when Chip Enable and Write Enable are at VIL with Output Enable at VIH. Commands, Input Data and Addresses are latched on the rising edge of Write Enable or Chip Enable, whichever occurs first.
See Figures 9 and 10, Write AC Waveforms, and Tables 13 and 14, Write AC Characteristics, for details of the timing requirements. Output Disable. The data outputs are high impedance when the Output Enable is at VIH. Standby. Standby disables most of the internal circuitry allowing a substantial reduction of the current consumption. The memory is in stand-by when Chip Enable is at VIH and the device is in read mode. The power consumption is reduced to the stand-by level and the outputs are set to high impedance, independently from the Output Enable or Write Enable inputs. If Chip Enable switches to VIH during a program or erase operation, the device enters Standby mode when finished. Automatic Standby. Automatic Standby provides a low power consumption state during Read mode. Following a read operation, the device enters Automatic Standby after 150ns of bus inactivity, even if Chip Enable is low, VIL, and the supply current is reduced to IDD1. The data Inputs/Outputs will still output data. Reset. During Reset mode, when Output Enable is low, VIL, the memory is deselected and the outputs are high impedance. The memory is in Reset mode when Reset is at VIL. The power consumption is reduced to the Standby level, independently from the Chip Enable, Output Enable or Write Enable inputs. If Reset is pulled to VSS during a Program or Erase, this operation is aborted and the memory content is no longer valid.
Table 2. Bus Operations
Operation Read Write Output Disable Standby Reset E VIL VIL VIL VIH X G VIL VIH VIH X X W VIH VIL VIH X X RP VIH VIH VIH VIH VIL WP X X X X X VPP Don't Care VDD or VPPH Don't Care Don't Care Don't Care DQ0-DQ15 Data Output Data Input Hi-Z Hi-Z Hi-Z
Note: X = VIL or VIH, VPPH = 12V 5%.
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COMMAND INTERFACE All Bus Write operations to the memory are interpreted by the Command Interface. Commands consist of one or more sequential Bus Write operations. An internal Program/Erase Controller handles all timings and verifies the correct execution of the Program and Erase commands. The Program/Erase Controller provides a Status Register whose output may be read at any time, to monitor the progress of an operation, or the Program/ Erase states. See Appendix D, Table 29, Write State Machine Current/Next, for a summary of the Command Interface. The Command Interface is reset to Read mode when power is first applied, when exiting from Reset or whenever VDD is lower than VLKO. Command sequences must be followed exactly. Any invalid combination of commands will reset the device to Read mode. Refer to Table 3, Commands, in conjunction with the text descriptions below. Read Memory Array command The Read command returns the memory to its Read mode. One Bus Write cycle is required to issue the Read Memory Array command and return the memory to Read mode. Subsequent read operations will read the addressed location and output the data. When a device Reset occurs, the memory defaults to Read mode. Read Status Register Command The Status Register indicates when a program or erase operation is complete and the success or failure of the operation itself. Issue a Read Status Register command to read the Status Register's contents. Subsequent Bus Read operations read the Status Register, at any address, until another command is issued. See Table 7, Status Register Bits, for details on the definitions of the bits. The Read Status Register command may be issued at any time, even during a Program/Erase operation. Any Read attempt during a Program/ Erase operation will automatically output the content of the Status Register. Read Electronic Signature Command The Read Electronic Signature command reads the Manufacturer and Device Codes. The Read Electronic Signature command consists of one write cycle, a subsequent read will output the Manufacturer or the Device Code depending on the levels of A0. The Manufacturer Code is output when the address line A0 is at VIL, the Device Code is output when A0 is at VIH. Addresses A1A7 must be kept to VIL, other addresses are ignored. The codes are output on DQ0-DQ7 with DQ8-DQ15 at 00h. (see Table 4)
Read CFI Query Command The Read Query Command is used to read data from the Common Flash Interface (CFI) Memory Area, allowing programming equipment or applications to automatically match their interface to the characteristics of the device. One Bus Write cycle is required to issue the Read Query Command. Once the command is issued subsequent Bus Read operations read from the Common Flash Interface Memory Area. See Appendix B, Common Flash Interface, Tables 23, 24, 25, 26, 27 and 28 for details on the information contained in the Common Flash Interface memory area. Block Erase Command The Block Erase command can be used to erase a block. It sets all the bits within the selected block to '1'. All previous data in the block is lost. If the block is protected then the Erase operation will abort, the data in the block will not be changed and the Status Register will output the error. Two Bus Write cycles are required to issue the command. s The first bus cycle sets up the Erase command. s The second latches the block address in the internal state machine and starts the Program/ Erase Controller. If the second bus cycle is not Write Erase Confirm (D0h), Status Register bits b4 and b5 are set and the command aborts. Erase aborts if Reset turns to VIL. As data integrity cannot be guaranteed when the Erase operation is aborted, the block must be erased again. During Erase operations the memory will only accept the Read Status Register command and the Program/Erase Suspend command, all other commands will be ignored. Typical Erase times are given in Table 6, Program, Erase Times and Program/Erase Endurance Cycles. See Appendix C, Figure 19, Erase Flowchart and Pseudo Code, for the flowchart for using the Erase command. Program Command The memory array can be programmed word-byword. Two bus write cycles are required to issue the Program command. s The first bus cycle sets up the Program command. s The second latches the Address and the Data to be written and starts the Program/Erase Controller. During Program operations the memory will only accept the Read Status Register command and the Program/Erase Suspend command. All other
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commands will be ignored. Typical Program times are given in Table 6, Program, Erase Times and Program/Erase Endurance Cycles. Programming aborts if Reset goes to VIL. As data integrity cannot be guaranteed when the program operation is aborted, the block containing the memory location must be erased and reprogrammed. See Appendix C, Figure 16, Program Flowchart and Pseudo Code, for the flowchart for using the Program command. Double Word Program Command This feature is offered to improve the programming throughput, writing a page of two adjacent words in parallel.The two words must differ only for the address A0. Programming should not be attempted when VPP is not at VPPH. The command can be executed if VPP is below VPPH but the result is not guaranteed. Three bus write cycles are necessary to issue the Double Word Program command. s The first bus cycle sets up the Double Word Program command. s The second bus cycle latches the Address and the Data of the first word to be written. s The third bus cycle latches the Address and the Data of the second word to be written and starts the Program/Erase Controller. Read operations output the Status Register content after the programming has started. Programming aborts if Reset goes to VIL. As data integrity cannot be guaranteed when the program operation is aborted, the block containing the memory location must be erased and reprogrammed. See Appendix C, Figure 17, Double Word Program Flowchart and Pseudo Code, for the flowchart for using the Double Word Program command. Clear Status Register Command The Clear Status Register command can be used to reset bits 1, 3, 4 and 5 in the Status Register to `0'. One bus write cycle is required to issue the Clear Status Register command. The bits in the Status Register do not automatically return to `0' when a new Program or Erase command is issued. The error bits in the Status Register should be cleared before attempting a new Program or Erase command. Program/Erase Suspend Command The Program/Erase Suspend command is used to pause a Program or Erase operation. One bus write cycle is required to issue the Program/Erase command and pause the Program/Erase controller. During Program/Erase Suspend the Command Interface will accept the Program/Erase Resume, Read Array, Read Status Register, Read Electronic Signature and Read CFI Query commands. Additionally, if the suspend operation was Erase then the Program command will also be accepted. Only the blocks not being erased may be read or programmed correctly. During a Program/Erase Suspend, the device can be placed in a pseudo-standby mode by taking Chip Enable to VIH. Program/Erase is aborted if Reset turns to VIL. See Appendix C, Figure 18, Program Suspend & Resume Flowchart and Pseudo Code, and Figure 20, Erase Suspend & Resume Flowchart and Pseudo Code for flowcharts for using the Program/ Erase Suspend command. Program/Erase Resume Command The Program/Erase Resume command can be used to restart the Program/Erase Controller after a Program/Erase Suspend operation has paused it. One Bus Write cycle is required to issue the command. Once the command is issued subsequent Bus Read operations read the Status Register. See Appendix C, Figure 18, Program or Double Word Program Suspend & Resume Flowchart and Pseudo Code, and Figure 20, Erase Suspend & Resume Flowchart and Pseudo Code for flowcharts for using the Program/Erase Resume command. Block Protection Two parameter/lockable blocks (blocks #0 and #1) can be protected against Program or Erase operations. Unprotected blocks can be programmed or erased. To protect the two lockable blocks set Write Protect to VIL. When VPP is below VPPLK all blocks are protected. Any attempt to Program or Erase protected blocks will abort, the data in the block will not be changed and the Status Register outputs the error. Table 5, Memory Blocks Protection Truth Table, defines the protection methods.
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Table 3. Commands
Bus Write Operations Commands No. of Cycles 1st Cycle Bus Op.
Write Write Write Write Write Write Write Write Write Write
2nd Cycle Data
FFh 70h 90h 98h 20h 40h or 10h 30h 50h B0h D0h
3nd Cycle Data
Data Status Register Signature Query D0h Data Input Data Input Write Addr 2 Data Input
Addr
X X X X X X X X X X
Bus Op.
Read Read
Addr
Read Addr X Signature Addr (2) CFI Addr Block Addr Addr Addr 1
Bus Op.
Addr
Data
Read Memory Array Read Status Register Read Electronic Signature Read CFI Query Erase Program Double Word Program (3) Clear Status Register Program/Erase Suspend Program/Erase Resume
1+ 1+ 1+ 1+ 2 2 3 1 1 1
Read Read Write Write Write
Note: 1. X = Don't Care. 2. A0=VIL outputs Manufacturer code, A0=VIH outputs Device code. Address A7-A1 must be VIL. 3. Addr 1 and Addr 2 must be consecutive Addresses differing only for A0.
Table 4. Read Electronic Signature
Code Manufacture. Code M28W320CT Device Code M28W320CB
Note: RP = VIH.
Device
E VIL VIL VIL
G VIL VIL VIL
W VIH VIH VIH
A0 VIL VIH VIH
A1-A7 VIL VIL VIL
A8-A20 Don't Care Don't Care Don't Care
DQ0-DQ7 20h BCh BDh
DQ8-DQ15 00h 88h 88h
Table 5. Memory Blocks Protection Truth Table
VPP (1) X VIL VDD or VPPH (2) VDD or VPPH (2) RP VIL VIH VIH VIH WP (1) X X VIL VIH Lockable Blocks (blocks #0 and #1) Protected Protected Protected Unprotected Other Blocks Protected Protected Unprotected Unprotected
Note: 1. X = Don't Care 2. VPP must also be greater than the Program Voltage Lock Out VPPLK.
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Table 6. Program, Erase Times and Program/Erase Endurance Cycles
M28W320B Parameter Word Program Double Word Program Main Block Program VPP = VDD VPP = 12V 5% Parameter Block Program VPP = VDD VPP = 12V 5% Main Block Erase VPP = VDD VPP = 12V 5% Parameter Block Erase VPP = VDD Program/Erase Cycles (per Block) 100,000 0.8 10 s cycles 1 0.8 10 10 s s 0.04 1 4 10 s s 0.32 0.02 5 4 s s Test Conditions VPP = VDD VPP = 12V 5% VPP = 12V 5% Unit Min Typ 10 10 0.16 Max 200 200 5 s s s
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STATUS REGISTER The Status Register provides information on the current or previous Program or Erase operation. The various bits convey information and errors on the operation. To read the Status register the Read Status Register command can be issued, refer to the Read Status Register Command section. To output the contents, the Status Register is latched on the falling edge of the Chip Enable or Output Enable signals, and can be read until Chip Enable or Output Enable returns to VIH. Either Chip Enable or Output Enable must be toggled to update the latched data. Bus Read operations from any address always read the Status Register during Program and Erase operations. The bits in the Status Register are summarized in Table 7, Status Register Bits. Refer to Table 7 in conjunction with the following text descriptions. Program/Erase Controller Status (Bit 7). The Program/Erase Controller Status bit indicates whether the Program/Erase Controller is active or inactive. When the Program/Erase Controller Status bit is Low (set to `0'), the Program/Erase Controller is active; when the bit is High (set to `1'), the Program/Erase Controller is inactive, and the device is ready to process a new command. The Program/Erase Controller Status is Low immediately after a Program/Erase Suspend command is issued until the Program/Erase Controller pauses. After the Program/Erase Controller pauses the bit is High . During Program, Erase, operations the Program/ Erase Controller Status bit can be polled to find the end of the operation. Other bits in the Status Register should not be tested until the Program/Erase Controller completes the operation and the bit is High. After the Program/Erase Controller completes its operation the Erase Status, Program Status, VPP Status and Block Protection Status bits should be tested for errors. Erase Suspend Status (Bit 6). The Erase Suspend Status bit (set to `1') indicates that an Erase operation has been suspended or is going to be suspended. The Erase Suspend Status should only be considered valid when the Program/Erase Controller Status bit is High (Program/Erase Controller inactive). Bit 7 is set within 30s of the Program/Erase Suspend command being issued therefore the memory may still complete the operation rather than entering the Suspend mode. When a Program/Erase Resume command is issued the Erase Suspend Status bit returns Low. memory may still complete the operation rather
Erase Status (Bit 5). The Erase Status bit can be used to identify if the memory has failed to verify that the block has erased correctly. When the Erase Status bit is High (set to `1'), the Program/ Erase Controller has applied the maximum number of pulses to the block and still failed to verify that the block has erased correctly. The Erase Status bit should be read once the Program/Erase Controller Status bit is High (Program/Erase Controller inactive). Once set High, the Erase Status bit can only be reset Low by a Clear Status Register command or a hardware reset. If set High it should be reset before a new Program or Erase command is issued, otherwise the new command will appear to fail. Program Status (Bit 4). The Program Status bit is used to identify a Program failure. When the Program Status bit is High (set to `1'), the Program/Erase Controller has applied the maximum number of pulses to the byte and still failed to verify that it has programmed correctly. The Program Status bit should be read once the Program/Erase Controller Status bit is High (Program/Erase Controller inactive). Once set High, the Program Status bit can only be reset Low by a Clear Status Register command or a hardware reset. If set High it should be reset before a new command is issued, otherwise the new command will appear to fail. VPP Status (Bit 3). The VPP Status bit can be used to identify an invalid voltage on the VPP pin during Program and Erase operations. The VPP pin is only sampled at the beginning of a Program or Erase operation. Indeterminate results can occur if VPP becomes invalid during an operation. When the VPP Status bit is Low (set to `0'), the voltage on the VPP pin was sampled at a valid voltage; when the VPP Status bit is High (set to `1'), the VPP pin has a voltage that is below the VPP Lockout Voltage, VPPLK, the memory is protected and Program and Erase operations cannot be performed. Once set High, the VPP Status bit can only be reset Low by a Clear Status Register command or a hardware reset. If set High it should be reset before a new Program or Erase command is issued, otherwise the new command will appear to fail. Program Suspend Status (Bit 2). The Program Suspend Status bit (set to `1') indicates that a Program operation has been suspended or is going to be suspended. The Program Suspend Status should only be considered valid when the Program/Erase Controller Status bit is High (Program/Erase Controller inactive). Bit 2 is set within 5s of the Program/Erase Suspend command being issued therefore the than entering the Suspend mode.
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When a Program/Erase Resume command is issued the Program Suspend Status bit returns Low. Block Protection Status (Bit 1). The Block Protection Status bit can be used to identify if a Program or Erase operation has tried to modify the contents of a protected block. When the Block Protection Status bit is High (set to `1'), a Program or Erase operation has been attempted on a protected block. Table 7. Status Register Bits
Bit 7 Name P/E.C. Status '0' '1' 6 Erase Suspend Status '0' '1' 5 Erase Status '0' '1' 4 Program Status '0' '1' 3 VPP Status '0' '1' 2 Program Suspend Status '0' '1' 1 0 Block Protection Status '0' Reserved No operation to protected blocks In Progress or Completed Program/Erase on protected Block, Abort Program Success VPP Invalid, Abort VPP OK Suspended Erase Success Program Error In progress or Completed Erase Error Busy Suspended Logic Level '1' Ready Definition
Once set High, the Block Protection Status bit can only be reset Low by a Clear Status Register command or a hardware reset. If set High it should be reset before a new command is issued, otherwise the new command will appear to fail. Reserved (Bit 0). Bit 0 of the Status Register is reserved. Its value must be masked. Note: Refer to Appendix C, Flowcharts and Pseudo Codes, for using the Status Register.
Note: Logic level '1' is High, '0' is Low.
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MAXIMUM RATING Stressing the device above the rating listed in the Absolute Maximum Ratings table may cause permanent damage to the device. Exposure to Absolute Maximum Rating conditions for extended periods may affect device reliability. These are stress ratings only and operation of the device at Table 8. Absolute Maximum Ratings
Value Symbol TA TBIAS TSTG VIO VDD, VDDQ VPP Parameter Min Ambient Operating Temperature (1) Temperature Under Bias Storage Temperature Input or Output Voltage Supply Voltage Program Voltage -40 -40 -55 -0.6 -0.6 -0.6 Max 85 125 155 VDDQ+0.6 4.1 13 C C C V V V Unit
these or any other conditions above those indicated in the Operating sections of this specification is not implied. Refer also to the STMicroelectronics SURE Program and other relevant quality documents.
Note: 1. Depends on range.
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DC AND AC PARAMETERS This section summarizes the operating and measurement conditions, and the DC and AC characteristics of the device. The parameters in the DC and AC characteristics Tables that follow, are derived from tests performed under the Measure-
ment Conditions summarized in Table 9, Operating and AC Measurement Conditions. Designers should check that the operating conditions in their circuit match the measurement conditions when relying on the quoted parameters.
Table 9. Operating and AC Measurement Conditions
M28W320BT, M28W320BB 70 Parameter Min VDD Supply Voltage VDDQ Supply Voltage (VDDQ VDD) Ambient Operating Temperature Load Capacitance (CL) Input Rise and Fall Times Input Pulse Voltages Input and Output Timing Ref. Voltages 2.7 2.7 - 40 50 5 0 to VDDQ VDDQ/2 Max 3.6 3.6 85 Min 2.7 2.7 - 40 50 5 0 to VDDQ VDDQ/2 Max 3.6 3.6 85 Min 2.7 2.7 - 40 50 5 0 to VDDQ VDDQ/2 Max 3.6 3.6 85 Min 2.7 1.65 - 40 50 5 0 to VDDQ VDDQ/2 Max 3.6 3.6 85 V V C pF ns V V 85 90 100 Units
Figure 6. AC Measurement I/O Waveform
Figure 7. AC Measurement Load Circuit
VDDQ
VDDQ VDDQ/2 0V
AI00610
VDDQ VDD 25k DEVICE UNDER TEST 0.1F 0.1F CL 25k
CL includes JIG capacitance
AI00609C
Table 10. Device Capacitance
Symbol CIN COUT Parameter Input Capacitance Output Capacitance Test Condition VIN = 0V VOUT = 0V Min Max 6 12 Unit pF pF
Note: Sampled only, not 100% tested.
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Table 11. DC Characteristics
Symbol ILI ILO IDD IDD1 IDD2 Parameter Input Leakage Current Output Leakage Current Supply Current (Read) Supply Current (Stand-by or Automatic Stand-by) Supply Current (Reset) Test Condition 0V VIN VDDQ 0V VOUT VDDQ E = VSS, G = VIH, f = 5MHz E = VDDQ 0.2V, RP = VDDQ 0.2V RP = VSS 0.2V Program in progress VPP = 12V 5% Program in progress VPP = VDD Erase in progress VPP = 12V 5% Erase in progress VPP = VDD E = VDDQ 0.2V, Erase suspended VPP > VDD VPP VDD RP = VSS 0.2V Program in progress VPP = 12V 5% Program in progress VPP = VDD Erase in progress VPP = 12V 5% Erase in progress VPP = VDD -0.5 VDDQ 2.7V VDDQ 2.7V IOL = 100A, VDD = VDD min, VDDQ = VDDQ min IOH = -100A, VDD = VDD min, VDDQ = VDDQ min VDDQ -0.1 1.65 11.4 3.6 12.6 1 2 -0.5 VDDQ -0.4 0.7 VDDQ 10 15 15 10 10 5 5 Min Typ Max 1 10 20 50 50 20 20 20 20 50 400 5 5 10 5 10 5 0.4 0.8 VDDQ +0.4 VDDQ +0.4 0.1 Unit A A mA A A mA mA mA mA A A A A mA A mA A V V V V V V V V V V
IDD3
Supply Current (Program)
IDD4
Supply Current (Erase)
IDD5 IPP IPP1 IPP2
Supply Current (Program/Erase Suspend) Program Current (Read or Stand-by) Program Current (Read or Stand-by) Program Current (Reset)
IPP3
Program Current (Program)
IPP4
Program Current (Erase)
VIL VIH VOL VOH VPP1 VPPH VPPLK VLKO
Input Low Voltage Input High Voltage Output Low Voltage Output High Voltage Program Voltage (Program or Erase operations) Program Voltage (Program or Erase operations) Program Voltage (Program and Erase lock-out) VDD Supply Voltage (Program and Erase lock-out)
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Figure 8. Read AC Waveforms
tAVAV A0-A20 tAVQV E tELQV tELQX G tGLQV tGLQX DQ0-DQ15 VALID tGHQX tGHQZ tEHQX tEHQZ VALID tAXQX
ADDR. VALID CHIP ENABLE
OUTPUTS ENABLED
DATA VALID
STANDBY
AI03825b
Table 12. Read AC Characteristics
M28W320B Symbol tAVAV tAVQV tAXQX (1) tEHQX (1) tEHQZ (1) tELQV (2) tELQX (1) tGHQX (1) tGHQZ (1) tGLQV (2) tGLQX (1) Alt tRC tACC tOH tOH tHZ tCE tLZ tOH tDF tOE tOLZ Parameter 70 Address Valid to Next Address Valid Address Valid to Output Valid Address Transition to Output Transition Chip Enable High to Output Transition Chip Enable High to Output Hi-Z Chip Enable Low to Output Valid Chip Enable Low to Output Transition Output Enable High to Output Transition Output Enable High to Output Hi-Z Output Enable Low to Output Valid Output Enable Low to Output Transition Min Max Min Min Max Max Min Min Max Max Min 70 70 0 0 20 70 0 0 20 20 0 85 85 85 0 0 20 85 0 0 20 20 0 90 90 90 0 0 25 90 0 0 25 30 0 100 100 100 0 0 30 100 0 0 30 35 0 ns ns ns ns ns ns ns ns ns ns ns Unit
Note: 1. Sampled only, not 100% tested. 2. G may be delayed by up to tELQV - tGLQV after the falling edge of E without increasing tELQV.
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PROGRAM OR ERASE tAVAV VALID tAVWH tWHAX
A0-A20
E tWHEH
tELWL
G tWHWL tWHGL
W tWLWH tWHEL tWHDX COMMAND CMD or DATA STATUS REGISTER tELQV
Figure 9. Write AC Waveforms, Write Enable Controlled
tDVWH
DQ0-DQ15
tWPHWH
tQVWPL
WP
tVPHWH
tQVVPL
VPP
SET-UP COMMAND
CONFIRM COMMAND OR DATA INPUT
STATUS REGISTER READ 1st POLLING
AI03826b
M28W320BT, M28W320BB
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Table 13. Write AC Characteristics, Write Enable Controlled
M28W320B Symbol tAVAV tAVWH tDVWH tELWL tELQV tQVVPL (1,2) tQVWPL tVPHWH (1) tWHAX tWHDX tWHEH tWHEL tWHGL tWHWL tWLWH tWPHWH tWPH tWP tVPS tAH tDH tCH Alt tWC tAS tDS tCS Write Cycle Time Address Valid to Write Enable High Data Valid to Write Enable High Chip Enable Low to Write Enable Low Chip Enable Low to Output Valid Output Valid to VPP Low Output Valid to Write Protect Low VPP High to Write Enable High Write Enable High to Address Transition Write Enable High to Data Transition Write Enable High to Chip Enable High Write Enable High to Chip Enable Low Write Enable High to Output Enable Low Write Enable High to Write Enable Low Write Enable Low to Write Enable High Write Protect High to Write Enable High Parameter 70 Min Min Min Min Min Min Min Min Min Min Min Min Min Min Min Min 70 45 45 0 70 0 0 200 0 0 0 25 20 25 45 45 85 85 45 45 0 85 0 0 200 0 0 0 25 20 25 45 45 90 90 50 50 0 90 0 0 200 0 0 0 30 30 30 50 50 100 100 50 50 0 100 0 0 200 0 0 0 30 30 30 50 50 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Unit
Note: 1. Sampled only, not 100% tested. 2. Applicable if VPP is seen as a logic input (VPP < 3.6V).
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PROGRAM OR ERASE tAVAV VALID tAVEH tEHAX
A0-A20
W tEHWH
tWLEL
G tEHEL tEHGL
E tELEH tEHDX COMMAND tWPHEH CMD or DATA STATUS REGISTER tQVWPL tELQV
tDVEH
Figure 10. Write AC Waveforms, Chip Enable Controlled
DQ0-DQ15
WP
tVPHEH
tQVVPL
VPP
POWER-UP AND SET-UP COMMAND
CONFIRM COMMAND OR DATA INPUT
STATUS REGISTER READ 1st POLLING
AI033827b
M28W320BT, M28W320BB
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Table 14. Write AC Characteristics, Chip Enable Controlled
M28W320B Symbol tAVAV tAVEH tDVEH tEHAX tEHDX tEHEL tEHGL tEHWH tELEH tELQV tQVVPL (1,2) tQVWPL tVPHEH (1) tWLEL tWPHEH tVPS tCS tWH tCP Alt tWC tAS tDS tAH tDH tCPH Write Cycle Time Address Valid to Chip Enable High Data Valid to Chip Enable High Chip Enable High to Address Transition Chip Enable High to Data Transition Chip Enable High to Chip Enable Low Chip Enable High to Output Enable Low Chip Enable High to Write Enable High Chip Enable Low to Chip Enable High Chip Enable Low to Output Valid Output Valid to VPP Low Data Valid to Write Protect Low VPP High to Chip Enable High Write Enable Low to Chip Enable Low Write Protect High to Chip Enable High Parameter 70 Min Min Min Min Min Min Min Min Min Min Min Min Min Min Min 70 45 45 0 0 25 25 0 45 70 0 0 200 0 45 85 85 45 45 0 0 25 25 0 45 85 0 0 200 0 45 90 90 50 50 0 0 30 30 0 50 90 0 0 200 0 50 100 100 50 50 0 0 30 30 0 50 100 0 0 200 0 50 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Unit
Note: 1. Sampled only, not 100% tested. 2. Applicable if VPP is seen as a logic input (VPP < 3.6V).
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Figure 11. Power-Up and Reset AC Waveforms
W, E, G
tPHWL tPHEL tPHGL
tPHWL tPHEL tPHGL
RP tVDHPH VDD, VDDQ Power-Up Reset
AI03453b
tPLPH
Table 15. Power-Up and Reset AC Characteristics
M28W320B Symbol Parameter Test Condition 70 tPHWL tPHEL tPHGL tPLPH(1,2) tVDHPH(3) During Program and Erase others Reset Low to Reset High Supply Voltages High to Reset High Min Min Min Min 50 30 100 50 85 50 30 100 50 90 50 30 100 50 100 50 30 100 50 s ns ns s Unit
Reset High to Write Enable Low, Chip Enable Low, Output Enable Low
Note: 1. The device Reset is possible but not guaranteed if tPLPH < 100ns. 2. Sampled only, not 100% tested. 3. It is important to assert RP in order to allow proper CPU initialization during power up or reset.
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PACKAGE MECHANICAL Figure 12. TSOP48 - 48 lead Plastic Thin Small Outline, 12 x 20mm, Package Outline
A2
1 N
e E B
N/2
D1 D
A CP
DIE
C
TSOP-a
Note: Drawing is not to scale.
A1
L
Table 16. TSOP48 - 48 lead Plastic Thin Small Outline, 12 x 20mm, Package Mechanical Data
Symbol A A1 A2 B C D D1 E e L N CP 0.50 0.05 0.95 0.17 0.10 19.80 18.30 11.90 - 0.50 0 48 0.10 mm Typ Min Max 1.20 0.15 1.05 0.27 0.21 20.20 18.50 12.10 - 0.70 5 0.0197 0.0020 0.0374 0.0067 0.0039 0.7795 0.7205 0.4685 - 0.0197 0 48 0.0039 Typ inches Min Max 0.0472 0.0059 0.0413 0.0106 0.0083 0.7953 0.7283 0.4764 - 0.0279 5
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Figure 13. TFBGA47 6.39x10.5mm - 8x6 ball array, 0.75mm pitch, Bottom View Package Outline
D D1 FD SD
FE
SE E E1
BALL "A1"
e ddd e b A2 A1
A
BGA-Z16
Drawing is not to scale.
Table 17. TFBGA47 6.39x10.5mm - 8x6 ball array, 0.75mm pitch, Package Mechanical Data
mm Symbol Typ A A1 A2 b D D1 ddd e E E1 FD FE SD SE 0.750 10.500 3.750 0.570 3.375 0.375 0.375 - 10.400 - - - - - 0.400 6.390 5.250 0.350 6.290 - 0.200 1.000 0.450 6.490 - 0.100 - 10.600 - - - - - 0.0295 0.4134 0.1476 0.0224 0.1329 0.0148 0.0148 - 0.4094 - - - - - 0.0157 0.2516 0.2067 0.0138 0.2476 - Min Max 1.200 0.0079 0.0394 0.0177 0.2555 - 0.0039 - 0.4173 - - - - - Typ Min Max 0.0472 inch
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Figure 14. TFBGA47 Daisy Chain - Package Connections (Top view through package)
1 2 3 4 5 6 7 8
A
B
C
D
E
F
AI03295
Figure 15. TFBGA47 Daisy Chain - PCB Connections proposal (Top view through package)
1 2 3 4 5 6 7 8
A
START POINT
B
C
D
E
F
END POINT
AI03296
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PART NUMBERING Table 18. Ordering Information Scheme
Example: Device Type M28 Operating Voltage W = VDD = 2.7V to 3.6V; VDDQ = 1.65V to 3.6V Device Function 320B = 32 Mbit (x16), Boot Block Array Matrix T = Top Boot B = Bottom Boot Speed 70 = 70 ns 85 = 85 ns 90 = 90 ns 100 = 100 ns Package N = TSOP48: 12 x 20 mm ZB = TFBGA47: 6.39 x 10.5mm, 0.75 mm pitch Temperature Range 1 = 0 to 70 C 6 = -40 to 85 C Option T = Tape & Reel Packing M28W320BT 90 N 6 T
Table 19. Daisy Chain Ordering Scheme
Example: Device Type M28W320B Daisy Chain -ZB = TFBGA47: 6.39 x 10.5mm, 0.75 mm pitch Option T = Tape & Reel Packing M28W320B -ZB T
Note:Devices are shipped from the factory with the memory content bits erased to '1'. For a list of available options (Speed, Package, etc...) or for further information on any aspect of this device, please contact the ST Sales Office nearest to you.
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M28W320BT, M28W320BB
REVISION HISTORY Table 20. Document Revision History
Date January 2001 06-Mar-2001 10-May-2001 29-May-2001 31-Oct-2001 16-May-2002 Version -01 -02 -03 -04 -05 -06 First Issue Document type : from Preliminary Data to Data Sheet 70ns Speed Class added Completely rewritten and restructured, 85ns speed class added. Corrections to CFI data and Block Address Table. VDDQ Maximum changed to 3.3V Commands Table, Read CFI Query Address on 1st cycle changed to `X' (Table 3) tWHEL description clarified (Table 13) VDDQ Maximum changed to 3.6V, TFBGA package dimensions added to description. Revision Details
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APPENDIX A. BLOCK ADDRESS TABLES Table 21. Top Boot Block Addresses, M28W320BT
# 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 Size (KWord) 4 4 4 4 4 4 4 4 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 Address Range 1FF000-1FFFFF 1FE000-1FEFFF 1FD000-1FDFFF 1FC000-1FCFFF 1FB000-1FBFFF 1FA000-1FAFFF 1F9000-1F9FFF 1F8000-1F8FFF 1F0000-1F7FFF 1E8000-1EFFFF 1E0000-1E7FFF 1D8000-1DFFFF 1D0000-1D7FFF 1C8000-1CFFFF 1C0000-1C7FFF 1B8000-1BFFFF 1B0000-1B7FFF 1A8000-1AFFFF 1A0000-1A7FFF 198000-19FFFF 190000-197FFF 188000-18FFFF 180000-187FFF 178000-17FFFF 170000-177FFF 168000-16FFFF 160000-167FFF 158000-15FFFF 150000-157FFF 148000-14FFFF 140000-147FFF 138000-13FFFF 130000-137FFF 128000-12FFFF 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 120000-127FFF 118000-11FFFF 110000-117FFF 108000-10FFFF 100000-107FFF 0F8000-0FFFFF 0F00000-F7FFF 0E8000-0EFFFF 0E0000-0E7FFF 0D8000-0DFFFF 0D0000-0D7FFF 0C8000-0CFFFF 0C0000-0C7FFF 0B8000-0BFFFF 0B0000-0B7FFF 0A8000-0AFFFF 0A0000-0A7FFF 098000-09FFFF 090000-097FFF 088000-08FFFF 080000-087FFF 078000-07FFFF 070000-077FFF 068000-06FFFF 060000-067FFF 058000-05FFFF 050000-057FFF 048000-04FFFF 040000-047FFF 038000-03FFFF 030000-037FFF 028000-02FFFF 020000-027FFF 018000-01FFFF 010000-017FFF 008000-00FFFF 000000-007FFF
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Table 22. Bottom Boot Block Addresses, M28W320BB
# 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 Size (KWord) 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 Address Range 1F8000-1FFFFF 1F0000-1F7FFF 1E8000-1EFFFF 1E0000-1E7FFF 1D8000-1DFFFF 1D0000-1D7FFF 1C8000-1CFFFF 1C0000-1C7FFF 1B8000-1BFFFF 1B0000-1B7FFF 1A8000-1AFFFF 1A0000-1A7FFF 198000-19FFFF 190000-197FFF 188000-18FFFF 180000-187FFF 178000-17FFFF 170000-177FFF 168000-16FFFF 160000-167FFF 158000-15FFFF 150000-157FFF 148000-14FFFF 140000-147FFF 138000-13FFFF 130000-137FFF 128000-12FFFF 120000-127FFF 118000-11FFFF 110000-117FFF 108000-10FFFF 100000-107FFF 0F8000-0FFFFF 0F0000-0F7FFF 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 4 4 4 4 4 4 4 4 0E8000-0EFFFF 0E0000-0E7FFF 0D8000-0DFFFF 0D0000-0D7FFF 0C8000-0CFFFF 0C0000-0C7FFF 0B8000-0BFFFF 0B0000-0B7FFF 0A8000-0AFFFF 0A0000-0A7FFF 098000-09FFFF 090000-097FFF 088000-08FFFF 080000-087FFF 078000-07FFFF 070000-077FFF 068000-06FFFF 060000-067FFF 058000-05FFFF 050000-057FFF 048000-04FFFF 040000-047FFF 038000-03FFFF 030000-037FFF 028000-02FFFF 020000-027FFF 018000-01FFFF 010000-017FFF 008000-00FFFF 007000-007FFF 006000-006FFF 005000-005FFF 004000-004FFF 003000-003FFF 002000-002FFF 001000-001FFF 000000-000FFF
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APPENDIX B. COMMON FLASH INTERFACE (CFI) The Common Flash Interface is a JEDEC approved, standardized data structure that can be read from the Flash memory device. It allows a system software to query the device to determine various electrical and timing parameters, density information and functions supported by the memory. The system can interface easily with the device, enabling the software to upgrade itself when necessary. When the CFI Query Command (RCFI) is issued the device enters CFI Query mode and the data Table 23. Query Structure Overview
Offset 00h 10h 1Bh 27h P A Reserved CFI Query Identification String System Interface Information Device Geometry Definition Primary Algorithm-specific Extended Query table Alternate Algorithm-specific Extended Query table Sub-section Name Description Reserved for algorithm-specific information Command set ID and algorithm data offset Device timing & voltage information Flash device layout Additional information specific to the Primary Algorithm (optional) Additional information specific to the Alternate Algorithm (optional)
structure is read from the memory. Tables 23, 24, 25, 26, 27 and 28 show the addresses used to retrieve the data. The CFI data structure also contains a security area where a 64 bit unique security number is written (see Table 28, Security Code area). This area can be accessed only in Read mode by the final user. It is impossible to change the security number after it has been written by ST. Issue a Read command to return to Read mode.
Note: Query data are always presented on the lowest order data outputs.
Table 24. CFI Query Identification String
Offset 00h 01h 02h-0Fh 10h 11h 12h 13h 14h 15h 16h 17h 18h 19h 1Ah Data 0020h 88BCh 88BDh reserved 0051h 0052h 0059h 0003h 0000h offset = P = 0035h 0000h 0000h 0000h value = A = 0000h 0000h Alternate Vendor Command Set and Control Interface ID Code second vendor - specified algorithm supported (note: 0000h means none exists) Address for Alternate Algorithm extended Query table note: 0000h means none exists NA Manufacturer Code Device Code Reserved Query Unique ASCII String "QRY" Query Unique ASCII String "QRY" Query Unique ASCII String "QRY" Primary Algorithm Command Set and Control Interface ID code 16 bit ID code defining a specific algorithm "Q" "R" "Y" Intel Compatible Description Value ST Top Bottom
Address for Primary Algorithm extended Query table
P=35h
NA
Note: Query data are always presented on the lowest order data outputs (DQ7-DQ0) only. DQ8-DQ15 are `0'.
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Table 25. CFI Query System Interface Information
Offset 1Bh Data 0027h Description VDD Logic Supply Minimum Program/Erase or Write voltage bit 7 to 4 BCD value in volts bit 3 to 0 BCD value in 100 mV VDD Logic Supply Maximum Program/Erase or Write voltage bit 7 to 4 BCD value in volts bit 3 to 0 BCD value in 100 mV VPP [Programming] Supply Minimum Program/Erase voltage bit 7 to 4 HEX value in volts bit 3 to 0 BCD value in 100 mV VPP [Programming] Supply Maximum Program/Erase voltage bit 7 to 4 HEX value in volts bit 3 to 0 BCD value in 100 mV Typical timeout per single word program = 2n s Typical timeout for Double Word Program = 2n s Typical timeout per individual block erase = 2n ms Typical timeout for full chip erase = 2n ms Maximum timeout for word program = 2n times typical Maximum timeout for Double Word Program = 2n times typical Maximum timeout per individual block erase = 2n times typical Maximum timeout for chip erase = 2n times typical Value 2.7V
1Ch
0036h
3.6V
1Dh
00B4h
11.4V
1Eh 1Fh 20h 21h 22h 23h 24h 25h 26h
00C6h 0004h 0004h 000Ah 0000h 0005h 0005h 0003h 0000h
12.6V 16s 16s 1s NA 512s 512s 8s NA
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Table 26. Device Geometry Definition
Offset Word Mode 27h 28h 29h 2Ah 2Bh 2Ch Data 0016h 0001h 0000h 0002h 0000h 0002h Description Device Size = 2n in number of bytes Flash Device Interface Code description Maximum number of bytes in multi-byte program or page = 2n Number of Erase Block Regions within the device. It specifies the number of regions within the device containing contiguous Erase Blocks of the same size. Region 1 Information Number of identical-size erase block = 003Eh+1 Region 1 Information Block size in Region 1 = 0100h * 256 byte Region 2 Information Number of identical-size erase block = 0007h+1 Region 2 Information Block size in Region 2 = 0020h * 256 byte Region 1 Information Number of identical-size erase block = 0007h+1 Region 1 Information Block size in Region 1 = 0020h * 256 byte Region 2 Information Number of identical-size erase block = 003Eh+1 Region 2 Information Block size in Region 2 = 0100h * 256 byte Value 4MByte x16 Async 4 2
2Dh 2Eh M28W320BT 2Fh 30h 31h 32h 33h 34h 2Dh 2Eh M28W320BB 2Fh 30h 31h 32h 33h 34h
003Eh 0000h 0000h 0001h 0007h 0000h 0020h 0000h 0007h 0000h 0020h 0000h 003Eh 0000h 0000h 0001h
63 64KByte 8 8KByte 8 8KByte 63 64KByte
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Table 27. Primary Algorithm-Specific Extended Query Table
Offset P = 35h (1) (P+0)h = 35h (P+1)h = 36h (P+2)h = 37h (P+3)h = 38h (P+4)h = 39h (P+5)h = 3Ah (P+6)h = 3Bh (P+7)h = 3Ch (P+8)h = 3Dh Data 0050h 0052h 0049h 0031h 0030h 0006h 0000h 0000h 0000h Major version number, ASCII Minor version number, ASCII Extended Query table contents for Primary Algorithm. Address (P+5)h contains less significant byte. bit 0 bit 1 bit 2 bit 3 bit 4 bit 31 to 5 Chip Erase supported Erase Suspend supported Program Suspend Lock/Unlock supported Queued Erase supported Reserved; undefined bits are `0' (1 (1 (1 (1 (1 = Yes, 0 = No) = Yes, 0 = No) = Yes, 0 = No) = Yes, 0 = No) = Yes, 0 = No) No Yes Yes No No Primary Algorithm extended Query table unique ASCII string "PRI" Description Value "P" "R" "I" "1" "0"
(P+9)h = 3Eh
0001h
Supported Functions after Suspend Read Array, Read Status Register and CFI Query are always supported during Erase or Program operation bit 0 bit 7 to 1 Program supported after Erase Suspend (1 = Yes, 0 = No) Reserved; undefined bits are `0' Yes NA
(P+A)h = 3Fh (P+B)h = 40h
0000h 0000h
Block Lock Status Defines which bits in the Block Status Register section of the Query are implemented. bit 0 Block Lock Status Register Lock/Unlock bit active(1 = Yes, 0 = No) bit 1 Block Lock Status Register Lock-Down bit active (1 = Yes, 0 = No) bit 15 to 2 Reserved for future use; undefined bits are `0'
(P+C)h = 41h
0030h
VDD Logic Supply Optimum Program/Erase voltage (highest performance) bit 7 to 4 bit 3 to 0 HEX value in volts BCD value in 100 mV
3V
(P+D)h = 42h
00C0h
VPP Supply Optimum Program/Erase voltage bit 7 to 4 bit 3 to 0 HEX value in volts BCD value in 100 mV
12V
(P+E)h
0000h
Reserved
Note: 1. See Table 24, offset 15h for P pointer definition.
Table 28. Security Code Area
Offset 81h 82h 83h 84h Data XXXX XXXX XXXX XXXX 64 bits unique device number. Description
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APPENDIX C. FLOWCHARTS AND PSEUDO CODES Figure 16. Program Flowchart and Pseudo Code
Start
Write 40h or 10h
program_command (addressToProgram, dataToProgram) {: writeToFlash (any_address, 0x40) ; /*or writeToFlash (any_address, 0x10) ; */ writeToFlash (addressToProgram, dataToProgram) ; /*Memory enters read status state after the Program Command*/ do { status_register=readFlash (any_address) ; /* E or G must be toggled*/
Write Address & Data
Read Status Register
b7 = 1 YES b3 = 0 YES b4 = 0 YES b1 = 0 YES End
NO } while (status_register.b7== 0) ;
NO
VPP Invalid Error (1, 2)
if (status_register.b3==1) /*VPP invalid error */ error_handler ( ) ;
NO
Program Error (1, 2)
if (status_register.b4==1) /*program error */ error_handler ( ) ;
NO
Program to Protected Block Error (1, 2)
if (status_register.b1==1) /*program to protect block error */ error_handler ( ) ;
}
AI03538b
Note: 1. Status check of b1 (Protected Block), b3 (VPP Invalid) and b4 (Program Error) can be made after each program operation or after a sequence. 2. If an error is found, the Status Register must be cleared before further Program/Erase Controller operations.
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Figure 17. Double Word Program Flowchart and Pseudo Code
Start
Write 30h
Write Address 1 & Data 1 (3)
Write Address 2 & Data 2 (3)
double_word_program_command (addressToProgram1, dataToProgram1, addressToProgram2, dataToProgram2) { writeToFlash (any_address, 0x30) ; writeToFlash (addressToProgram1, dataToProgram1) ; /*see note (3) */ writeToFlash (addressToProgram2, dataToProgram2) ; /*see note (3) */ /*Memory enters read status state after the Program command*/ do { status_register=readFlash (any_address) ; /* E or G must be toggled*/
Read Status Register
b7 = 1 YES b3 = 0 YES b4 = 0 YES b1 = 0 YES End
NO } while (status_register.b7== 0) ;
NO
VPP Invalid Error (1, 2)
if (status_register.b3==1) /*VPP invalid error */ error_handler ( ) ;
NO
Program Error (1, 2)
if (status_register.b4==1) /*program error */ error_handler ( ) ;
NO
Program to Protected Block Error (1, 2)
if (status_register.b1==1) /*program to protect block error */ error_handler ( ) ;
}
AI03539b
Note: 1. Status check of b1 (Protected Block), b3 (VPP Invalid) and b4 (Program Error) can be made after each program operation or after a sequence. 2. If an error is found, the Status Register must be cleared before further Program/Erase operations. 3. Address 1 and Address 2 must be consecutive addresses differing only for bit A0.
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Figure 18. Program Suspend & Resume Flowchart and Pseudo Code
Start program_suspend_command ( ) { writeToFlash (any_address, 0xB0) ; writeToFlash (any_address, 0x70) ; /* read status register to check if program has already completed */ Write 70h do { status_register=readFlash (any_address) ; /* E or G must be toggled*/
Write B0h
Read Status Register
b7 = 1 YES b2 = 1 YES Write FFh
NO
} while (status_register.b7== 0) ;
NO
Program Complete
if (status_register.b2==0) /*program completed */ { writeToFlash (any_address, 0xFF) ; read_data ( ) ; /*read data from another block*/ /*The device returns to Read Array (as if program/erase suspend was not issued).*/
Read data from another address
} else { writeToFlash (any_address, 0xFF) ; read_data ( ); /*read data from another address*/ writeToFlash (any_address, 0xD0) ; /*write 0xD0 to resume program*/ } } Read Data
Write D0h
Write FFh
Program Continues
AI03540b
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Figure 19. Erase Flowchart and Pseudo Code
Start erase_command ( blockToErase ) { writeToFlash (any_address, 0x20) ; writeToFlash (blockToErase, 0xD0) ; /* only A12-A20 are significannt */ /* Memory enters read status state after the Erase Command */
Write 20h
Write Block Address & D0h
Read Status Register
do { status_register=readFlash (any_address) ; /* E or G must be toggled*/
b7 = 1
NO } while (status_register.b7== 0) ;
YES b3 = 0 YES b4, b5 = 1 NO b5 = 0 YES b1 = 0 YES End }
AI03541b
NO
VPP Invalid Error (1)
if (status_register.b3==1) /*VPP invalid error */ error_handler ( ) ;
YES
Command Sequence Error (1)
if ( (status_register.b4==1) && (status_register.b5==1) ) /* command sequence error */ error_handler ( ) ;
NO
Erase Error (1)
if ( (status_register.b5==1) ) /* erase error */ error_handler ( ) ;
NO
Erase to Protected Block Error (1)
if (status_register.b1==1) /*program to protect block error */ error_handler ( ) ;
Note: If an error is found, the Status Register must be cleared before further Program/Erase operations.
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Figure 20. Erase Suspend & Resume Flowchart and Pseudo Code
Start
Write B0h
erase_suspend_command ( ) { writeToFlash (any_address, 0xB0) ; writeToFlash (any_address, 0x70) ; /* read status register to check if erase has already completed */
Write 70h
Read Status Register
do { status_register=readFlash (any_address) ; /* E or G must be toggled*/ NO } while (status_register.b7== 0) ;
b7 = 1 YES b6 = 1 YES Write FFh
NO
Erase Complete
if (status_register.b6==0) /*erase completed */ { writeToFlash (any_address, 0xFF) ;
read_data ( ) ; /*read data from another block*/ /*The device returns to Read Array (as if program/erase suspend was not issued).*/
Read data from another block or Program else Write D0h Write FFh
} { writeToFlash (any_address, 0xFF) ; read_program_data ( ); /*read or program data from another address*/ writeToFlash (any_address, 0xD0) ; /*write 0xD0 to resume erase*/ } }
Erase Continues
Read Data
AI03549b
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APPENDIX D. COMMAND INTERFACE AND PROGRAM/ERASE CONTROLLER STATE Table 29. Write State Machine Current/Next
Command Input (and Next State) Current State SR bit 7 Data When Read Read Array (FFh) Read Array Read Array Read Array Program Setup (10/40h) Program Setup Program Setup Program Setup Erase Setup (20h) Erase Setup Erase Setup Erase Setup Erase Confirm (D0h) Program/ Program/ Erase Erase Suspend Resume (B0h) (D0h) Read Array Read Array Read Array Read Status (70h) Read Status Read Status Read Status Clear Status (50h) Read Array Read Array Read Array Read Elect.Sg. (90h) Read Elect.Sg. Read Elect.Sg. Read Elect.Sg.
Read Array Read Status Read Elect.Sg. Program Setup Program (continue) Program Suspend to Read Status Program Suspend to Read Array Program Suspend to Read Elect.Sg. Program (complete) Erase Setup Erase Cmd. Error Erase (continue) Erase Suspend to Read Status Erase Suspend to Read Array Erase Suspend to Read Elect.Sg. Erase (complete)
"1" "1" "1" "1"
Array Status Electronic Signature Status
Program (Command input = Data to be Programmed) Program Suspend to Read Status Program (continue) Program Suspend to Read Array Program Suspend to Read Array Program Suspend to Read Array Read Array Erase Erase Erase Command (continue) (continue) Error Read Array Erase Suspend to Read Status Erase (continue) Erase Suspend to Read Array Erase Suspend to Read Array Erase Suspend to Read Array Read Array Erase (continue) Program (continue)
"0"
Status
Program (continue)
Program (continue)
"1"
Status
Program Suspend to Read Array Program Suspend to Read Array Program Suspend to Read Array Read Array
Program Suspend to Read Array
Program Suspend to Read Status Program Suspend to Read Status Program Suspend to Read Status Read Status
Program Suspend to Read Array Program Suspend to Read Array Program Suspend to Read Array Read Array
Program Suspend to Read Elect.Sg. Program Suspend to Read Elect.Sg. Program Suspend to Read Elect.Sg. Read Elect.Sg.
"1"
Array
Program Suspend to Read Array
Program (continue)
Program (continue)
"1"
Electronic Signature
Program Suspend to Read Array Program Setup Erase Setup
Program (continue)
Program (continue)
"1"
Status
"1"
Status
Erase Command Error
Erase Command Error
"0"
Status
Read Array
Program Setup
Erase Setup
Read Status
Read Array
Read Elect.Sg.
"1"
Status
Erase (continue)
Erase (continue)
"1"
Status
Erase Suspend to Read Array Erase Suspend to Read Array Erase Suspend to Read Array Read Array
Program Setup
Erase Suspend to Read Array Erase Suspend to Read Array Erase Suspend to Read Array Erase Setup
Erase Suspend to Read Status Erase Suspend to Read Status Erase Suspend to Read Status Read Status
Erase Suspend to Read Array Erase Suspend to Read Array Erase Suspend to Read Array Read Array
Erase Suspend to Read Elect.Sg. Erase Suspend to Read Elect.Sg. Erase Suspend to Read Elect.Sg. Read Elect.Sg.
"1"
Array
Program Setup
Erase (continue)
Erase (continue)
"1"
Electronic Signature
Program Setup Program Setup
Erase (continue)
Erase (continue)
"1"
Status
Note: Elect.Sg. = Electronic Signature.
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Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. The ST logo is registered trademark of STMicroelectronics All other names are the property of their respective owners. (c) 2002 STMicroelectronics - All Rights Reserved STMicroelectronics GROUP OF COMPANIES Australia - Brazil - Canada- China - Finland - France - Germany - Hong Kong - India - Italy - Japan - Malaysia - Malta - Morocco Singapore - Spain - Sweden - Switzerland - United Kingdom - U.S.A. www.st.com
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